As a personal note, I was listing out the considerations I do before floor planning of the PCB. Almost all these points should be kept in mind before planning to place the components as well as when you are doing the PCB layout. Here, at Leaf Design Lab, I take utmost care while designing the high-speed layouts of DRAMs, SRAMs, eMMCs, Ethernet and HDMIs with multi-core processors and avoid most of the EMC issues right the first time. Most of the issues can be taken care at the layout stage, but there are plenty during the components selection/ schematics preparation stage to take care, which I will list down in upcoming posts. Here we go:
1. Related to Ground Plane
- Avoid high Impedance Ground paths to components; thus increase the size of the ground plane (GND) as much as you can. An ideal way is to dedicate a whole layer for GND just beneath the decoupling in a multi-layer PCBs.
- Avoid Long Ground Loops, which in fact acts as an antenna and radiates the energy.
- Use more than 2 layer PCB for better EMC performance or Use ground grids for 2 Layer PCB (As per personal experience, this is difficult as you have very less freedom to route on 2 layer board already.)
4. Do not make the ground line common and terminate to ground. Use dedicated lines for the parallel components to connect to ground. Use separate vias for each ground termination, if there is a separate ground plane beneath as shown in the image here. [This is the 3D model of the same PCB in the cover image. See the Decoupling flower beneath "C" character in the image.]
5. High-Speed traces nearest reference plane to be solid ground to avoid impedance mismatches and thus avoiding ringing, reflections, undershoots or overshoots due to them. Check the PCB stack-up; if a high-speed signal layer is near to power plane, avoid the plane crossing.
2. Use Faraday cage surrounding whole board. Use via stitching to create a cage for internal emissions to be inside and external emission to be outside. No signal traces should be routed out of the Faraday cage. As shown in the images below, the faraday caging and via shielding is done. It should be done as per your manufacturer's capability keeping in mind that the tolerances and clearance constraints are met.
3. Layers and Power Plane: 20H Rule (Check my detailed post here for Faraday Caging and 20H rule)
4. Make Rooms and Place components as per segments. Use filters at the segment boundaries (Difficult to keep the filters for high-bit parallel lines due to tight real estate on the board and to reduce the overall system cost. Must if you are making a product of Med-Mil standard)
5. Use planned Board Stackup to avoid cross talks and to keep proper reference planes for high-speed traces. (It's a big topic in itself, so avoiding the explanation here)
6. Keep high-speed signals and clock traces as short as possible and keep them nearer to the ground plane (although, there is a trade-off between impedance matching and crosstalk for high-speed lines because of strict rules of transmission lines) and away from the board edge. Vias in such signal near the connector and PCB edge must be avoided. Keep away such signals from Power plane as well to reduce the inducing noise on power planes.
7. Differential lines must run in parallel to cancel the magnetic fields of these out-of-phase lines. Adjust/tune the length of shorter running differential line near the source by adding a small serpentine.
8. A return path of the signal should run closely in parallel with the associated signal trace to provide least reactance path creating the shortest current loop.
9. Keep Crystal oscillator traces very short and place such crystals near to the chip. Keep ground test point near to such crystals or oscillators, if in case there is a need to ground the body of a crystal during the testing period to check the changes in emissions.
10. Terminate the floating clocks with suitable matching termination network. Series termination, parallel, thavenin or AC termination, etc are the type of clock terminations. Series termination should be placed at the driver side. It consumes low power but increases rise and fall times of the signal. In most designs, 20ohms to 33ohms are enough for the series termination.
11. Avoid the impedance mismatches on clock lines (especially in high-speed/DDR clock lines) to avoid the reflections in the signal in form of radiations. Introduce the impedance matching on the traces by considering them as transmission lines over 30MHz. To match the impedance of these lines : Trace thickness, Ground Clearances, PCB stack, dielectric constants of the PCB materials and reference plane plays a crucial role. Highlighted differential lines in the image above are 100 Ohm impedance matched 4*16bit DDR3 DQS clock with air-gap of 5.3mils and trace thickness of 3.7mils.
12. Analog signals are highly affected by high-speed and switching signals. Guard the signal with the ground trace and stitch the ground trace with the vias to create a shielding for the analog signal. Do not share the ground planes of Analog and Digital subsystems, isolate them with inductor or ferrite bead. Following is the example of TWL6040 Audio Codec IC with analog and digital ground isolated by inductor/ferrite bead. **Please note that the signal is on layer 6 with a solid analog ground plane on layer 7 hence not crossing any planes. The analog and digital grounds are isolated on layer 2.
13. Noise coupled on the power supply rail is high frequency due to AC-DC and DC-DC switchers into the power management system. The decoupling capacitor provides a low-impedance path for high-frequency current and thus decouples such noise from power plane to the ground. Such capacitors should be placed inside 50mil area near the power pin of the processor. Use capacitor with low ESL and low ESR values. Moreover, choose the rated voltage of capacitor by 5-10 times of operating voltage to keep in mind the derating at certain voltages.
14. Add metallic shielding over potential emitting components or on the components to sustain the ambient radiation. Multiple shields can be added to a single board to attenuate the radiation from one region of the board on the other. This attenuates both E-field and H-field component of the radiated electromagnetic waves.
15. Use shielded cables for high-speed data lines or twisted pair cables. Use multiple return paths in a flat ribbon cable.
Not everytime you can address all the points to rectify the issues. Sometimes, there is a tight budget BoM or sometimes there can be real estate shortage on the board. Hope, you liked this article; it's been a long time since I have written an article here. Let me know if there are any of the top techniques that I have missed. I will keep updating the feed with different articles. You can discuss your EMC issues right here in the comment section or you can directly message me!
Cheers,
Rushi.
Cheers,
Rushi.
